`include "common_header.verilog"

//  *************************************************************************
//  File : bip_error_count_top_40g
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited.
//  Copyright (c) 2009 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Denis Poverennyy
//  info@morethanip.com
//  *************************************************************************
//  Description : Implement the 16-bit BIP8 error counters for each lane
//                with read mux and clear on read.
//  Version     : $Id: bip_error_count_top_40g.v,v 1.1 2011/01/19 21:24:47 wt Exp $
//  *************************************************************************

module bip_error_count_top_40g (

   reset_rx_clk,
   reset_reg_clk,
   rx_clk,
   reg_clk,
   sw_reset,
   bip8_stat_0,
   bip8_stat_1,
   bip8_stat_2,
   bip8_stat_3,
   reg_rd,
   reg_sel,
   reg_sel_vendor,
   cnt0,
   cnt1,
   cnt2,
   cnt3);
   
   
input   reset_rx_clk;   //  Asynchronous Reset - line clock Domain
input   reset_reg_clk;  //  Asynchronous Reset - reg_clk Domain
input   rx_clk;         //  XL/CGMII Receive Clock
input   reg_clk;        //  Register Interface Clock
input   sw_reset;       //  SW reset
input   bip8_stat_0;    //  BIP-8 error status lane 0
input   bip8_stat_1;    //  BIP-8 error status lane 1
input   bip8_stat_2;    //  BIP-8 error status lane 2
input   bip8_stat_3;    //  BIP-8 error status lane 3
input   reg_rd;         //  reading
input   [11:0] reg_sel; //  register address
input   reg_sel_vendor; //  select standard(0)/vendor(1) registers
output   [15:0] cnt0;   //  counter 0  
output   [15:0] cnt1;   //  counter 1  
output   [15:0] cnt2;   //  counter 2  
output   [15:0] cnt3;   //  counter 3 

//  register read data
wire    [15:0] cnt0; 
wire    [15:0] cnt1; 
wire    [15:0] cnt2; 
  
wire    [15:0] cnt3; 
wire    [3:0] read_mask; //  read per Register




//  reg_rd='0' and reg_rd_r='1' and reg_sel_reg=X"0C8" and reg_sel_vendor_reg='0'

assign read_mask[0] = reg_sel == 12'h 0C8 & reg_sel_vendor == 1'b 0 & reg_rd == 1'b 1 ? 1'b 1 : 1'b 0; 
assign read_mask[1] = reg_sel == 12'h 0C9 & reg_sel_vendor == 1'b 0 & reg_rd == 1'b 1 ? 1'b 1 : 1'b 0; 
assign read_mask[2] = reg_sel == 12'h 0CA & reg_sel_vendor == 1'b 0 & reg_rd == 1'b 1 ? 1'b 1 : 1'b 0; 
assign read_mask[3] = reg_sel == 12'h 0CB & reg_sel_vendor == 1'b 0 & reg_rd == 1'b 1 ? 1'b 1 : 1'b 0; 


bip_error_count_single_lane U_BIP_ERR_CNT_0 (

          .reset_rx_clk(reset_rx_clk),
          .reset_reg_clk(reset_reg_clk),
          .rx_clk(rx_clk),
          .reg_clk(reg_clk),
          .sw_reset(sw_reset),
          .bip8_stat(bip8_stat_0),
          .reg_rd(read_mask[0]),
          .bip_cnt_rdata(cnt0));
          
          
bip_error_count_single_lane U_BIP_ERR_CNT_1 (

          .reset_rx_clk(reset_rx_clk),
          .reset_reg_clk(reset_reg_clk),
          .rx_clk(rx_clk),
          .reg_clk(reg_clk),
          .sw_reset(sw_reset),
          .bip8_stat(bip8_stat_1),
          .reg_rd(read_mask[1]),
          .bip_cnt_rdata(cnt1));
          
          
bip_error_count_single_lane U_BIP_ERR_CNT_2 (

          .reset_rx_clk(reset_rx_clk),
          .reset_reg_clk(reset_reg_clk),
          .rx_clk(rx_clk),
          .reg_clk(reg_clk),
          .sw_reset(sw_reset),
          .bip8_stat(bip8_stat_2),
          .reg_rd(read_mask[2]),
          .bip_cnt_rdata(cnt2));
          
          
bip_error_count_single_lane U_BIP_ERR_CNT_3 (

          .reset_rx_clk(reset_rx_clk),
          .reset_reg_clk(reset_reg_clk),
          .rx_clk(rx_clk),
          .reg_clk(reg_clk),
          .sw_reset(sw_reset),
          .bip8_stat(bip8_stat_3),
          .reg_rd(read_mask[3]),
          .bip_cnt_rdata(cnt3));

endmodule // module bip_error_count_top_40g

